(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which is constituted mainly by field effect transistors (FETs) and use of which speeds up and stabilizes the read operation in the device.
(2) Description of the Related Art
Conventionally, in a semiconductor device of the kind to which the present invention relates, a plurality of memory elements are arranged in a matrix form, and a gate, a drain and a source of each of the memory elements are connected to a word line, a digit line and ground, respectively.
In the foregoing semiconductor device, when an address data is inputted to the semiconductor device, one of the memory elements is selected by one word line and one digit line which are made active by the address data.
Further, for writing the data, a threshold voltage of a high level or a low level is selectively assigned to the memory elements. That is, where, when data is written, a voltage of the select word line is V.sub.G, a threshold voltage of the low level is V.sub.TL, and a threshold voltage of the high level is V.sub.TH, these voltages will be set as follows: EQU V.sub.TL =2 V&lt;V.sub.G =5 V&lt;V.sub.TH =7 V.
The read circuit for the foregoing memory elements is, as shown in FIG. 1, constituted by a pull-up transistor Q.sub.1 for a memory element M1, a pull-up transistor Q.sub.6 and a pull-down transistor Q.sub.5 for generating a reference voltage, and a differential amplifier 1 for amplifying and outputting a difference in voltages applied to one input terminal S1 and the other input terminal S2. In this circuit, the memory element M1 is selected by the select word line W1 and the select digit line D1.
Here, if the threshold voltage V.sub.M of the memory element M1 is higher than the voltage V.sub.G of the select digit line, i.e., V.sub.G &lt;V.sub.M, the memory element M1 becomes non-conductive, and the select digit line D1 is made equilibrium at a high level voltage V.sub.H by the pull-up transistor Q.sub.1 which is in a conductive state. The memory element M1 under this state is called "OFF-bit".
On the other hand, if the threshold voltage V.sub.M of the memory element M1 is lower than the voltage V.sub.G of the select digit line, i.e., V.sub.M &lt;V.sub.G, the memory element M1 becomes conductive and, thus, the select digit line D1 is made equilibrium at a low level voltage V.sub.L which is lower than the above high level voltage V.sub.H. The memory element M1 under this state is called "ON-bit".
Thus, the voltage of the select digit line D1 in the case where the selected memory element M1 is "OFF-bit" and that in the case where the same is "ON-bit" are different from each other. However, since the difference between the high level voltage V.sub.H and the low level voltage V.sub.L is as small as 1 V, generally a differential amplifier 1 is used in order to speedily amplify to, for example, a 5 V amplitude which is a CMOS level amplitude.
The select digit line D1 is connected to one input terminal S1 of the differential amplifier 1 and a reference voltage V.sub.R is applied to the other input terminal S2 thereof. Here, the reference voltage V.sub.R is set in advance to an intermediate voltage between the high level voltage V.sub.H and the low level voltage V.sub.L, which can be expressed as follows: EQU V.sub.L &lt;V.sub.R &lt;V.sub.H.
If the voltage V.sub.S1 of the select digit line D1 is lower than the reference voltage V.sub.R, i.e., V.sub.S1 &lt;V.sub.R, the output voltage V.sub.SO at an output terminal SO of the differential amplifier 1 will be at ground level (0 V). If the voltage V.sub.S1 of the select digit line D1 is higher than the reference voltage V.sub.R, i.e., V.sub.R &lt;V.sub.S1, the output voltage V.sub.SO of the differential amplifier 1 will be at a power supply V.sub.CC level (=5 V)
Details as to how the high level voltage V.sub.H, the low level voltage V.sub.L and the reference voltage V.sub.R are set are explained using the current-voltage characteristics of the pull-up transistor Q.sub.1 and the memory element M1 shown in FIG. 2 and also the current-time characteristics at the output terminal SO of the differential amplifier 1 shown in FIG. 3.
If the pull-up transistor Q.sub.1 is an N-channel enhancement mode transistor and its gate and drain are commonly connected to the power supply source V.sub.CC, the current-voltage characteristics of the pull-up transistor Q.sub.1 will be as shown by I.sub.1 in FIG. 2.
On the other hand, if the memory element M1 is made an N-channel enhancement mode transistor and its gate is applied with a voltage V.sub.G of the select word line W1, the current-voltage characteristics of the memory element M1 in the case of "ON-bit" will be as shown by I.sub.M1 in FIG. 2.
When the memory element M1 is in the "OFF-bit", no current flows in the memory element M1. Thus, specific values of the high level voltage V.sub.H and the low level voltage V.sub.L are calculated from the current-voltage characteristics I.sub.1 of the pull-up transistor Q.sub.1 and the current-voltage characteristics I.sub.M1 of the memory element M1.
Specifically, the low level voltage V.sub.L is calculated from the crossing point of the current-voltage characteristics I.sub.1 of the pull-up transistor Q.sub.1 and the current-voltage characteristics I.sub.M1 of the memory element M1. Also, the high level voltage V.sub.H is calculated from the current-voltage characteristics I.sub.1 of the pull-up transistor Q.sub.1 when the current does not flow therethrough (FIG. 2).
Here, the high level voltage V.sub.H may be expressed as: EQU V.sub.H =V.sub.CC -V.sub.TN,
wherein V.sub.TN is a threshold voltage of the N-channel transistor.
Where it is preferable to set the reference voltage V.sub.R such that, as seen in FIG. 3, the inversion speed T.sub.INV(H) of the differential amplifier 1 for a high level output and the inversion speed T.sub.INV(L) for a low level output become substantially the same, it may be set to: EQU V.sub.R =(V.sub.H +V.sub.L)/2.
In FIGS. 2 and 3, the reference voltage V.sub.R calculated from this equation is shown by V.sub.RM. The aforementioned technology has been disclosed in Japanese Patent Application Kokai Publication No. Hei 3-142790.
The method (circuit means) to be employed for generating the reference voltage V.sub.R is optional, but the exemplified method shown here is one in which the pull-up transistor Q.sub.6 and the pull-down transistor Q.sub.5 are caused to become conductive simultaneously.
In the foregoing conventional semiconductor device, the inversion speed of the differential amplifier at low level output is greatly dependent on or influenced by the time required for discharging the digit line through the memory element, hence by the current capability of the memory element.
However, in a semiconductor device having a large storage capacity, for example, a ROM (read only memory) having a memory data of 16 mega-bytes, since importance is attached to high integration of the device, the channel width of a memory element is extremely fine.
For the above reason, the current capability of the memory element is only about 10 .mu.A whereas the current capability of other transistors is in the order of mA. Thus, the discharging speed of the select digit line, hence the inversion speed of the differential amplifier at a low level output, becomes extremely low.
On the other hand, the inversion speed of the differential amplifier at a high level output is largely dependent on or influenced by the time required for charging the select digit line through the pull-up transistor, hence by the current capability of the pull-up transistor.
However, if the current capability of the pull-up transistor is designed to be large, a voltage difference between voltages during "ON-bit" selection and "OFF-bit" selection in the select digit line becomes small, resulting in a lack of stability in the operation of the differential amplifier.
Furthermore, if the current capability of the pull-up transistor is too large with respect to the memory element, the select digit line will be excessively charged, leading to a problem that the next low level output cannot be effected.
Under the above circumstances, there will be no alternative but to set the current capability of the pull-up transistor to such an extremely small value of the order of .mu.A as in the case of the memory element, in which case the charging speed of the select digit line, hence the inversion speed of the differential amplifier for a high level output, becomes extremely low.
As explained above, the conventional semiconductor device suffers from a problem that, since the charging and discharging speeds of the select digit line, that is, the inversion speeds of the differential amplifier, are extremely low, the device is not suited to applications in which high speed performance is required.